1. Field of the Invention
The present invention relates to a semiconductor device suitable for composing CMOS (complementary metal-oxide semiconductor) and a method of manufacturing thereof.
2. Description of the Related Art
General procedures for manufacturing conventional CMOS transistor are as follows. FIGS. 15A through 17C are schematic sectional views serially showing process steps of a conventional method of manufacturing a CMOS transistor.
First as shown in FIG. 15A, an element isolation region 4 is formed in the surficial portion of a P-type semiconductor substrate 1, and wells are then formed in the device forming areas partitioned by the element isolation region 4, where a P-well 2 is formed in an N-channel MOS (NMOS) area, and an N-well 3 is formed in a P-channel MOS (PMOS) area.
Next as shown in FIG. 15B, an insulating film and a polysilicon film are formed on the semiconductor substrate 1, and then patterned to thereby form gate insulating films 5 and gate electrodes 6, respectively, in the device forming areas.
Next as shown in FIG. 15C, a resist film 21 is formed so as to cover the PMOS area and to expose the NMOS area. Using the resist film 21 and gate electrode 6 together as a mask, arsenic is ion-implanted at a high concentration to thereby form extension layers 11 in the P-well 2, and then boron or indium is ion-implanted to thereby form pocket layers 9 deeper in the P-well 2. Ion implantation of boron or indium herein is carried out from a direction normal to or declined away from the surface of the semiconductor substrate 1.
Next as shown in FIG. 16A, the resist film 21 is removed, and a resist film 22 is formed so as to cover the NMOS area and to expose the PMOS area. Using the resist film 22 and gate electrode 6 together as a mask, boron is ion-implanted at a high concentration to thereby form extension layers 12 in the N-well 3, and then arsenic is ion-implanted to thereby form pocket layers 10 deeper in the N-well 3. Ion implantation of arsenic herein is carried out from a direction normal to or declined away from the surface of the semiconductor substrate 1.
Next as shown in FIG. 16B, the resist film 22 is removed, an insulating film is formed over the entire surface, and the film is then anisotropically etched so as to leave a portion of such film only on the side surfaces of the gate electrodes 6, to thereby form side walls 13.
Next as shown in FIG. 16C, a resist film 25 is formed on the semiconductor substrate 1 so as to cover the PMOS area and to expose the NMOS area. Using the resist film 25, gate electrode 6 and side walls 13 together as a mask, arsenic is ion-implanted at a high concentration to thereby form deep source/drain diffusion regions 14.
Next as shown in FIG. 17A, the resist film 25 is removed, and a resist film 26 is formed on the semiconductor substrate 1 so as to cover the NMOS area and to expose the PMOS area. Using the resist film 26, gate electrode 6 and side walls 13 together as a mask, boron is ion-implanted at a high concentration to thereby form deep source/drain diffusion regions 15.
Then as shown in FIG. 17B, the resist film 26 is removed, and a silicide layer, which is typically a cobalt silicide layer 16, is then formed on the gate electrodes 6 and source/drain diffusion regions 14 and 15.
This process successfully yields a CMOS transistor.
The foregoing process however suffers from a drawback such that the resist films 21, 22 used as the masks when the pocket layers and extension layers are formed must be removed after these layers are formed, where ashing or wet treatment required for removing the resist films 21, 22 inevitably oxidizes the silicon substrate. Oxidation of the silicon substrate results in loss of the implanted impurities, which fails in attaining an expected concentration and profile. Oxidation of the silicon substrate is also disadvantageous in that making the extension layers distant from the gate portion to thereby substantially deepen junction of the extension layers. This undesirably causes degradation of the characteristics, which is typified by short-channel effect.
Another disadvantage of the above-described manufacturing method relates to annealing which is necessary for activating impurities in the source/drain region 15 after the formation thereof, where the annealing undesirably promotes outward diffusion of impurities which reside in the channel to thereby cause depletion of the channel, or undesirably promotes outward diffusion of impurities which reside in the source/drain diffusion region 15.
There is known a technique for suppressing the outward diffusion, which is an oxide film capping based on RTO (rapid thermal oxidation). Another known technique relates to formation of an outward diffusion preventive film, which is typified by a nitride film having a thickness of 100 nm or around formed by CVD process. The oxide film capping, however, suffers from a drawback such that profile of the source/drain diffusion layer becomes deeper due to accelerated diffusion induced by oxygen. On the other hand, formation of the nitride film having a thickness of 100 nm or around on the side surfaces of the gate electrode by the CVD process tends to result in increased stress and abnormal diffusion.